1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device incorporating capacitors based on a high-dielectric film material.
2. Description of the Related Art
Workstations and personal computers have their main memories based on DRAM (Dynamic Random Access Memory) chips. A DRAM chip consists of a plurality of (e.g., 64 Mega bits) memory cells, each storing 1-bit binary data. Each memory cell consists of a MOS (Metal Oxide Semiconductor) transistor and a capacitor. The memory cell stores 1-bit data in terms of whether or not the capacitor is charged. The conduction of charges through the MOS transistor between the capacitor and the bit line, which has been precharged to the precharge voltage and thereafter brought to the floating state, causes the bit line voltage to vary. For reading out 1-bit data from the memory cell, a voltage difference between the bit line voltage and the precharge voltage is amplified by a sense amplifier in connection with the bit line.
A voltage difference emerging on the bit line at reading out data from the memory cell must be competent against the noise on the bit line and to meet the sensitivity of sense amplifier. In other words, the capacitor of memory cell must have a capacitance large enough to cause a certain voltage difference to arise at data reading. However, due to the ever increasing scale of integration and capacity of DRAM chips, the capacitor electrodes become smaller. In dealing with this trend, there is practiced a large scale production of DRAM chips employing memory cells of stack type or trench type in which the capacitor electrodes have a sufficient area by extending vertically in the semiconductor substrate. At the same time, research and development are under way for forming capacitors of memory cells with a dielectric film material having a large dielectric constant so that a large capacitance per unit area is accomplished.
FIG. 5 shows the cross section of a conventional DRAM chip having capacitors formed of dielectric film material with a large dielectric constant. In the figure, on one major surface of a p-type semiconductor substrate 1, there are formed n-type MOS transistors 2 each having a source/drain region 2a, another source/drain region 2b and a gate electrode 2e. The gate electrode 2e is formed to confront a channel region 2c between the two source/drain regions 2a and 2b with a gate insulation film 2d interposed therebetween. Gate electrodes 2e are part of word lines running in parallel to one another. A device separation region 3 is formed of an oxide film. Similarly, part of word lines 4 serve as gate electrodes of other MOS transistors (not shown). An oxide film 5 is formed to cover the gate electrodes 2e and word lines 4, and it has the formation of a contact hole 6 above the other source/drain region 2b.
A buried bit line 7 of polycrystalline silicon (poly-Si) is formed on the oxide film 5, and it is connected to the other source/drain region 2b through the contact hole 6. An insulating layer 8 is formed to cover the buried bit line 7. An inter-layer insulation film 9 of BPSG (Boro-Phospho Silicate Glass) film having a planar upper surface is formed on the entire substrate 1. A contact hole 10 is formed to run through the inter-layer insulation film 9 and reach the surface of the one source/drain region 2a. A plug 11 of Poly-Si is formed to fill the interior of the contact hole 10 and to be connected to the one source/drain region 2a.
One capacitor electrode 12 of platinum (Pt) is formed on the inter-layer insulation film 9, and it is connected to the one source/drain region 2a through the plug 11 in the contact hole 10. A dielectric film 13 of high-dielectric material SrTiO.sub.3 for making a capacitor is formed by being in contact with the upper and side surfaces of the one capacitor electrode 12. Another capacitor electrode 14 of platinum (Pt) is formed to confront the one capacitor electrode 12 by being interposed with the capacitor dielectric film 13. Accordingly, the electrodes 12 and 14 and dielectric film 13 in unison constitute a capacitor. The one capacitor electrode 12 is made from platinum so that the dielectric film 13 has a normal crystal structure of high-dielectric material SrTiO.sub.3.
An inter-layer insulation film 15 having a planar upper surface is formed on the entire surface of the other capacitor electrode 14. Wiring strips 16 of aluminum (Al) are formed on the inter-layer insulation film 15. Another inter-layer insulation film 17 is formed to cover the entire surface of the wiring strips 16. Other wiring strips 18 of aluminum are formed on the inter-layer insulation film 17 to extend perpendicularly to the wiring strips 16.
In the foregoing conventional DRAM chip incorporating capacitors formed of high-dielectric films, the one capacitor electrode 12 of platinum is in direct contact with the inter-layer insulation film 9 of BPSG and the plug 11 for connecting the electrode 12 to the one source/drain region 2a. Therefore, constituent atoms, other than platinum, of the inter-layer insulation film 9 and plug 11 (e.g., silicon atoms of the plug 11) diffuse into the one capacitor electrode 12 of platinum. This gives rise to such a problem that the capacitor dielectric film 13 cannot have a normal crystal structure.
In order to solve this problem, there has been proposed a DRAM chip structure as shown in FIG. 6. This DRAM chip is different from the one shown in FIG. 5 in that one capacitor electrode 12 consists of a high-layer electrode 12a of platinum and a low-layer electrode 12b which is formed between the high-layer electrode 12a and the inter-layer insulation film 9 and plug 11 and adapted to serve as a barrier.
However, this improved DRAM chip shown in FIG. 6 has its composition of crystal structure varied at the portion of the capacitor dielectric film 13 in contact with the side surface of the low-layer electrode 12b, resulting in deteriorated insulation characteristics of that portion. This gives rise to the emergence of a leakage current flowing between the side surface of the low-layer electrode 12b and the other capacitor electrode 14, resulting in deteriorated data holding characteristics of the memory cell.